Author: Stefan Hunsche et al.
Description: The usage of conventional OPC models traditionally was confined to the specific process conditions at which the models
were. Separable models for computational lithography (CL), including OPC and post-OPC layout verification, allow
extrapolation of the calibrated model and accurate prediction at process conditions different from the exact settings used
for model calibration. This capability enables significantly reduced turnaround time in early process development, and it
opens the way for new applications such as model based process optimization. It relies on sufficiently accurate modeling
of litho process components as separate subsystems, in particular mask, scanner optics, and resist process. Inclusion of
actual machine parameters of the exposure tool in the optical model can improve model accuracy and predictability,
while actual machine parameters may represent either a specific scanner type or an individual exposure tool. We study
the impact of machine parameters that can be incorporated in a modern computational litho model, by analyzing their
relative effect on predicted CD measurements and extract a ranking in terms of their expected benefit for model
separability. An experimental study demonstrates improved model accuracy and separability by inclusion of either
scanner-type specific model data or individual machine-specific metrology data in the CL model building process.

Author: George Chen et al.
Description: The minimum feature size of integrated circuit continues to shrink. At 32 nm and smaller nodes, mask linearity
errors caused by short range proximity effects less than around 3um during the manufacturing of photomasks
become more significant in the overall lithography error budget. To address this, we have carried out a study that:
(1). models the short range mask error; (2). implements mask process correction (MPC) based on these mask error
models; and (3). verifies the mask process corrections. In this paper we will demonstrate that application of MPC
can significantly reduce mask errors with minimal increase in writing overhead.

Author: Tadahiro Takigawa et al.
Description: In the continuous battle to improve critical dimension (CD) uniformity, especially for 45-nanometer (nm) logic
advanced products, one important recent advance is the ability to accurately predict the mask CD uniformity
contribution to the overall global wafer CD error budget. In most wafer process simulation models, mask error
contribution is embedded in the optical and/or resist models. We have separated the mask effects, however, by
creating a short-range mask process model (MPM) for each unique mask process and a long-range CD
uniformity mask bias map (MBM) for each individual mask. By establishing a mask bias map, we are able to
incorporate the mask CD uniformity signature into our modelling simulations and measure the effects on global
wafer CD uniformity and hotspots. We also have examined several ways of proving the efficiency of this
approach, including the analysis of OPC hot spot signatures with and without the mask bias map (see Figure 1)
and by comparing the precision of the model contour prediction to wafer SEM images. In this paper we will
show the different steps of mask bias map generation and use for advanced 45nm logic node layers, along with
the current results of this new dynamic application to improve hot spot verification through Brion Technologies’
model-based mask verification loop.

Author: Hua-yu Liu et al.
Description: The challenge for the upcoming full-chip CD uniformity (CDU) control at 32nm and 22nm nodes is unprecedented with
expected specifications never before attempted in semiconductor manufacturing. To achieve these requirements, OPC models not only must be accurate for full-chip process window characterization for fine-tuning and matching of the existing processes and exposure tools, but also be trust-worthy and predictive to enable processes to be developed in advance of next-generation photomasks, exposure tools, and resists. This new OPC requirement extends beyond the intended application scope for behavior-lumped models. Instead, separable OPC models are better suited, such that each model stage represents the physics and chemistry more completely in order to maintain reliable prediction accuracy. The resist, imaging tool, and mask models must each stand independently, allowing existing resist and mask models to be combined with new optics models based on exposure settings other than the one calibrated previously. In this paper, we assess multiple sets of experimental data that demonstrate the ability of the Tachyon FEM (focus and exposure modeling) to separate the modeling of mask, optics, and resists. We examine the predictability improvements
of using 3D mask models to replace thin mask model and the use of measured illumination source versus top-hat types.
Our experimental wafer printing results show that OPC models calibrated in FEM to one optical setting can be
extrapolated to different optical settings, with prediction accuracy commensurate with the calibration accuracy. We see up to 45% improvement with the measured illumination source, and up to 30% improvement with 3D mask. Additionally, we observe evidence of thin mask resist models that are compensating for 3D mask effect in our wafer data by as much as 60%.

Author: D.H. Son et al.
Description: The semiconductor industry has been pushed to continue device scaling in order to improve chip density and
performance. A couple of researchers have developed source mask optimization (SMO) technique to maximize process
window. SMO is a method to optimize the illumination source and to perform optical proximity correction (OPC) of a critical pattern mask sequentially. In this paper, we exploited SMO technique as a new resolution enhancement technique (RET) solution for the contact hole layer of a 32nm node system-on-chip (SOC) device. SMO was applied to two kinds of layouts static random access memory (SRAM) and through-pitch contact patterns in order to consider different layout characteristics between logic and memory block in an SOC device. As a result of SMO for scalable and nonscalable diffraction optical element (DOE) with considering its manufacturability, it is shown that a hexapole DOE is one of the best sources for a contact layer of 32nm SOC device. Hexapole DOE optimized by SMO can improve imaging performance (e.g. normalized image log-slope (NILS), exposure latitude (EL)), as compared with annular DOE. Besides, it can provide sufficient process windows for the technology development of 32nm SOC device.
Keywords: Source mask optimization (SMO), Resolution enhancement technique (RET), System-on-chip (SOC),
contact layer

Author: J. Fung Chen et al.
Description: While lithography R&D community at large has already gotten the mind set for 32nm, all eyes are on 22nm node. Current consensus is to employ computational lithography to meet wafer CD uniformity (CDU) requirement. Resolution enhancement technologies (RET) and model OPC are the two fundamental components for computational lithography. Today’s full-chip CDU specifications are already pushing physical limits at extreme lithography k1 factor. While increasingly aggressive RET either by double exposure or double patterning are enabling imaging performance, for CDU control we need ever more accurate OPC at a greater computational efficiency.
In this report, we discuss the desire for wanting more robust and accurate OPC models. One important trend is to have predictive OPC models allowing accurate OPC results to be obtained much faster, shortening the qualification process for exposure tools. We investigate several key parameters constitute to accuracy achievable in computational lithography. Such as the choice of image pixel size, numbers of terms needed for transmission cross coefficients (TCC), and “safe” ambit radius for assuring accurate CD prediction. Selections of image pixel size and “safe” ambit radius together determine % utilization for 2D fast Fourier transformation (FFT) for efficient full-chip OPC computation. For IC manufacturing beyond ArF, we made initial observations and estimations on EUV computational lithography. These discussions pave the way for developing a computational lithography roadmap extends to the end of Moore’s Law. This computational lithography roadmap aims to be a complement for the current ITRS roadmap on what does it take to achieve CD correction accuracy.

Author: Vince Plachecki et al.
Description: The introduction of lithographic systems with NA=1.35 has enabled the extension of optical lithography to 45 nm and
below. At the same time, despite the larger NA, k1-factors have dropped to 0.3 and below. Defining the appropriate
strategies for these high-end lithographic processes requires the integration and co-optimization of the design, mask and
imaging parameters. This requires an in-depth understanding of the relevant parameters for imaging performance during
high volume manufacturing.
Besides the Critical Dimension Uniformity (CDU) budget for the baseline lithographic system, it is crucial to realize that
system performance may vary over time in volume manufacturing.
In this paper the CDU budget will be restated, with all the well-known contributors, and extended with some new terms,
such as volume manufacturing effects.
Experimental low-k1 results will be shown from NA=1.35 lithographic tools and compared to model-based predictions
under realistic volume manufacturing circumstances.
The combination of extreme NA and low k1 makes it necessary to introduce computational lithography for scanner
optimization. The potential of using LithoCruiserTM and TachyonTM for optimising scanner source and OPC will be
described. Also, using the fast scanner correction mechanisms to compensate for reticle, track and etch fingerprints and
variations will be discussed.
Keywords: simulations, lithographic predictions, hyper-NA, low k1

Author: Yu Cao et al.
Description: Optical lithography has had great success in recent history in utilizing the most advanced optical technology to create
NA=1.35 immersion lenses. These lenses have aberration levels at or below the 5m�� level. Much of this is due to
advancements in lens design, materials, and aspheric polishing techniques. Now that the lenses are nearly “perfect”,
more attention is being given to the illuminator and its performance. This paper examines the fundamental metrics that
are used to analyze the illumination source shape as it pertains to the optical proximity effect (OPE). It is found that the
more traditional metric of partial coherence, ��, is often not sufficient to explain through pitch CD performance. Metrics
are introduced to compare multiple sources and compared to their correlation to OPE with respect to a reference. A new
parametric model for annular illumination is introduced and shown to correlate within an RMS=0.03nm of the OPE data.

Author: Hong Chen et al.
Description: When using the most advanced water-based immersion scanner at the 32nm node half-pitch, the image resolution will be below the k1 limit of 0.25. If EUV technology is not ready for mass production, double patterning technology (DPT) is one of the solutions to bridge the gap between wet ArF and EUV platforms. DPT technology implies a patterning process with two photolithography/etching steps. As a result, the critical pitch is reduced by a factor of 2, which means the k1 value could increase by a factor of 2. Due to the superimposition of patterns printed by two separate patterning steps, the overlay capability, in addition to image capability, contributes to critical dimension uniformity (CDU). The wafer throughput as well as cost is a concern because of the increased number of process steps. Therefore, the performance of imaging, overlay, and throughput of a scanner must be improved in order to implement DPT cost effectively. In addition, DPT requires an innovative software to evenly split the patterns into two layers for the full chip. Although current electronic design automation (EDA) tools can split the pattern through abundant geometry-manipulation functions, these functions, however, are insufficient. A rigorous pattern split requires more DPT-specific functions such as tagging/grouping critical features with two colors (and hence two layers), controlling the coloring sequence, correcting the printing error on stitching boundaries, dealing with color conflicts, increasing the coloring accuracy, considering full-chip possibility, etc. Therefore, in this paper we cover these issues by demonstrating a newly developed DPT pattern-split algorithm using a rule-based method. This method has one strong advantage of achieving very fast processing speed, so a full-chip DPT pattern split is practical. After the pattern split, all of the color conflicts are highlighted. Some of the color conflicts can be resolved by aggressive model-based methods, while the un-resolvable conflicts, known as native conflicts, require a change in the design to achieve a DPT-friendly design. A model-based stitching boundary correction is then used after the color conflicts are corrected. Finally the OPC treatment is implemented on both split layouts. The OPC challenges are highlighted by examining the printed image from both exposures. The key concepts described above with additional full chip requirements have been successfully implemented onto Brion’s Tachyon™ system. The efficiency and accuracy of the DPT pattern split method were evaluated on a full-chip layout. The results show that the algorithm proposed in this paper is a viable solution for the DPT pattern split.

Author: Hua-yu Liu et al.
Description: Dimensions for 32nm generation logic are expected to be ~45nm. Even with high NA scanners, the k1 factor is below 0.32. Gridded-design-rules (GDR) are a form of restricted design rules (RDR) and have a number of benefits from design through fabrication. The combination of rules and topologies can be verified during logic technology development, much as is done with memories. Topologies which have been preverified can be used to implement random logic functions with “hotspot” prevention that is virtually context-independent. Mask data preparation is simplified with less aggressive OPC, resulting in shorter fracturing, writing, and inspection times. In the wafer fab, photolithography, etch, and CMP are more controllable because of the grating-like patterns. Tela Canvas GDR layout was found to give smaller area cells than a conventional 2D layout style. Variability and context independence were also improved.
Keywords: Low k1, gridded design rules, restricted design rules, context dependent hotspots

Author: Zongchang Yu et al.
Description: At 65nm technology node and below, with the ever-smaller process window, it is no longer sufficient to apply traditional model-based verification at only the nominal condition. Full-chip, full process-window verification has started to integrate into the OPC flow at the 65nm production as a way of preventing potentially weak post-OPC designs from reaching the mask making step. Through process-window analysis can be done by way of simulating wafer images at each of the corresponding focus and exposure dose conditions throughout the process window using an accurate and predictive FEM model. Alternatively, due to the strong correlation between the post-OPC design sensitivity to dose variation and aerial image (AI) quality, the study of through-dose behavior of the post-OPC design can also be carried out by carefully analyzing the AI. These types of analysis can be performed at multiple defocus conditions to assess the robustness of the post-OPC designs with respect to focus and dose variations. In this paper, we study the AI based approach for post-OPC verification in detail.
For metal layer, the primary metrics for verification are bridging, necking, and via coverage. In this paper we are mainly interested in studying bridging and necking. The minimum AI value in the open space gives an indication of its susceptibility to bridging in an over-dosed situation. Lower minimum intensity indicates less risk of bridging. Conversely, the maximum AI between the metal lines provides indication of potential necking issues in an under-dosed situation.
At times, however, in a complex 2D pattern area, the location as to where the AI reaches either maximum or minimum is not obvious. This requires a full-chip, dense image-based approach to fully explore the AI profile of the entire space of the design. We have developed such an algorithm to find the AI maximums and minimums that will bear true relevance to the bridging and necking analysis. In this paper, we apply the full-chip image-based analysis to 65nm metal layers. We demonstrate the capturing of potential bridging or necking issues as identified by the AI analysis. Finally, we show the performance of the full-chip image-based verification.
Keywords: OPC, Verification, Process Window, Image checker

Author: Peng Liu et al.
Description: The accuracy of a fast 3D thick mask model is evaluated for 6% AttPSM having sub-resolution assist features (SRAF).
The main features and SRAFs are designed to print 40nm lines or spaces on wafer (k1~0.28) through pitch from 100nm
to 500nm. The resulting optimum SRAF sizes vary from 10nm to 48nm depending on the main feature pitch, mask tone
and illuminator shape. The model accuracy is evaluated on both main feature CDs and SRAF side lobe intensities by
comparing with a rigorous model. The fast 3D model shows improvements in both areas over thin mask model,
particularly in SRAF printability prediction.

Author: Tony Vacca et al.
Description: One of the most critical points for accurate OPC is to have accurate models that properly simulate the full process from the mask fractured data to the etched remaining structures on the wafer. In advanced technology nodes, the CD error budget becomes so tight that it is becoming critical to improve modeling accuracy. Current technology models used for OPC generation and verification are mostly composed of an optical model, a resist model and sometimes an etch model. The mask contribution is nominally accounted for in the optical and resist portions of these models. Mask processing has become ever more complex throughout the years so properly modeling this portion of the process has the potential to improve the overall modeling accuracy. Also, measuring and tracking individual mask parameters such as CD bias can potentially improve wafer yields by detecting hotspots caused by individual mask characteristics. In this paper, we will show results of a new approach that incorporates mask process modeling. We will also show results of testing a new dynamic mask bias application used during OPC verification.

Author: Lynn Cai et al.
Description: As the semiconductor industry moves into 45nm process technology and beyond, design complexities increase exponentially. Lithographers also continue to implement more exotic resolution enhancement technologies to push patterning further beyond the physical limits. These complexities heighten the need for designers to take into consideration the lithography behavior of a design, a behavior which designers were not concerned with before. For example, designers need to make sure that the lithography process will not change the signal integrity of their design. It is extremely difficult to make changes in the design after tapeout and therefore it becomes very critical to do lithography compliance checking before tapeout.

Author: Mark Terry et al.
Description: Pushing optical microlithography towards the 32nm node requires hyper-NA immersion optics in combination with
advanced illumination, polarization, and mask technologies. Novel approaches in model-based optical proximity
correction (OPC) and sub-resolution assist feature (SRAF) optimization are required to not only produce correct feature shapes at the nominal process condition but also to maintain edge placement tolerances within spec limits under process variations in order to ensure a finite process window. In addition, it is becoming increasingly important to consider interactions between multiple layers when performing correction in order to ensure electrical viability. In this paper we discuss the application of a model based process-window-aware and interlayer-aware integrated OPC system on 32nm node patterns. Process window awareness will be demonstrated for main feature correction by taking into account image-based modeling at multiple defocus and dose conditions. In addition, interlayer-awareness will be demonstrated by correction that takes into account the effects of active width on gate CD and of contact overlap with metal, gate, and active. The results show an improvement over “non-aware” OPC in gate CD control, in contact overlap, and in overall process margin. In addition, PW aware correction is demonstrated to prevent potential catastrophic failures at extreme PW conditions.

Author: Peng Liu et al.
Description: A new framework has been developed to model 3D thick mask effects for full-chip OPC and verifications. In addition to
electromagnetic (EM) scattering effects, the new model also takes into account the non-Hopkins oblique incidence
effects commonly found in real lithography systems but missing in prior art. Evaluations against rigorous simulations and experimental data showed the new model provides improved accuracy, compared to both the thin-mask model and the thick-mask model based on Hopkins treatment of oblique incidence.

Author: Youping Zhang, et al.
Description: In this paper, we introduce a new Focus Exposure Matrix (FEM) model based on Brion’s Tachyon™ platform. The
FEM model has two adjustable parameters: focus and exposure. By adjusting these parameters, new models at arbitrary process conditions within the process window can be quickly derived, with which large number of simulation results can be obtained at different exposure and focus for detailed process window analysis. The fitting of FEM model is through a single calibration process using wafer measurements at limited number of sampling locations within the process window. The resulting calibrated FEM model is shown to have superior fitting as well as prediction accuracy, without requiring massive additional focus-exposure measurements.

Author: Amandine Borjon, et al.
Description: To verify the printability of a design across process window, compact optical models calibrated from experimental data measured at the limits of the process window are used. A comparison between the dry lithography process model and the immersion lithography process model is presented for the poly layer at 65 nm node patterning. Specific failure predictions obtained with the two processes are compared with experimental results.

Author: Luoqi Chen, et al.
Description: To minimize or eliminate lithography errors associated with optical proximity correction, integrated circuit
manufacturers need an accurate, predictive, full-chip lithography model which can account for the entire process window (PW). We have validated the predictive power of a novel focus-exposure modeling methodology with wafer data collected across the process window at multiple customer sites. Tachyon Focus-Exposure Modeling (FEM) first-principle, physics-driven simulations deliver accurate and predictive full-chip lithography modeling for producing state-of-the-art circuits.

Author: Jim Vasek, et al.
Description: Lithographic hot spots are identified on 90nm-node critical layers by the Brion Tachyon RDI system comparing the design intent GDS-II database to simulated resist contours. Selected hot spots are sent to the Applied Materials OPC Check system to create recipes to automatically drive a VeritySEM CD SEM for measurement and analysis. The model-predicted hot spots, combined with accurate wafer metrology, enable an efficient determination of the actual process window, including process-limiting features and manufacturing lithography conditions, for qualification and control of each layer.

Author: Yongfa Huang, et al.
Description: This paper demonstrates a novel approach to improve process window prediction capability. The new method, Lithography Manufacturability Check (LMC), is capable of predicting wafer level CDs across an entire chip and the lithography process window with a CD accuracy of better than 10nm. The advantages of LMC for full chip process window analysis as well as the MEEF check to catch process weak points are shown and the application to real designs are demonstrated.

Author: Patrick Martin, et al.
Description: Ever-decreasing lithography k1 values demand tighter design-to-manufacturing integration. To verify imaging performance, Photronics is exploring an application-specific-lithography computer, which achieves high accuracy, superior coverage, and orders-of-magnitude speed increases compared to current software simulation tools.

Author: Patrick Martin, et al.
Description: Two RET design checking flows are examined and compared. These RET design checking flows are implemented on new platform that combines a hardware accelerated computational engine with a new analysis method to numerically evaluate the lithographic printing and mask manufacturing challenges for a given design layout. Through the high speed computation of lithographic images from full chip data, many opportunities for novel and cost effective post layout lithography verification options become available.

Author: Yu Cao, et al.
Description: As the design complexity grows exponentially, pure software based simulation tools running on general-purpose computer clusters are facing increasing challenges in meeting today’s requirements for cycle time, coverage, and modeling accuracy. We have developed a new lithography simulation platform (Tachyon™) which achieves orders of magnitude speedup as compared to traditional pure software simulation tools. The platform combines innovations in all levels of the system: algorithm, software architecture, cluster-level architecture, and proprietary acceleration hardware using application specific integrated circuits.

Author: Stefan Hunsche, et al.
Description: We introduce a novel in-scanner aerial image sampling method. A sensor wafer records data at the wafer plane under production conditions. CD estimates are obtained from the image data. The linear sensor response provides complete information on the imaging process and contrast, ILS, or peak values. We characterize CD variations, repeatability, reproducibility of the system, and show its capability to detect changes in imaging performance in a production environment.

Author: Stefan Hunsche, et al.
Description: We present massively parallel sampling of aerial images at the wafer plane of a 193nm scanner. The system operates under exact production conditions with a high-resolution wafer-like sensor. We demonstrate image capturing and other capabilities of the system, using ~400,000 sampling points across the full exposure field. We show focus maps, CD measurements, sensitivity to sub-resolution features and aberrations, and excellent agreement with simulations.